Projects (until May-2017)
A 8GHz Bandwidth 50 - 500 ps True Time Delay Realization Using a Variable-Order All-pass Filter Architecture in TSMC 65nm process
Duration: June 2015 - June 2016
Guide: Prof. Nagendra Krishnapura, Electrical Engineering, IIT Madras
Antennas are one of the essential parts of wireless communication systems. They act as transducers to convert guided waves to radiated waves or vice versa in transmitters and receivers. The beam patterns of conventional antennas are fixed and unchangeable but in recent wireless communication systems some degree of reconfigurability is essential. Beamforming is a technique developed to provide reconfigurability in the beam patterns of the antennas. Beamforming antennas are implementable via phased array
antenna (PAA) systems. To change the beam pattern of the array, the PAA should delay and amplify the input signals by different
amounts so that they constructively interfere in one direction and destructively in other directions. So, there is a need for designing tunable delay elements for PAA systems. Their delay-range, noise, non-linearity, bandwidth, size, cost and power consumption have a dominant effect on the phased array antenna systems. There are different physical methods for the realization of on-chip time delay blocks like transmission lines, LC delay lines, active filters, digital delay blocks (digital filters and gates) and phase shifters.
Compact active true-time-delay lines can be realized using a high order Gm-C all-pass filter(APF) based on a singly-terminated ladder filter. Increased mismatch at small area is combated by calibrating all Gms at startup. We propose a digital calibration scheme to calibrate OTAs and proposed architecture enables 5x area reduction for the same mismatch. Coarse delay tuning is realized by changing the filter order and fine tuning by changing the gm. The delay line has 50-500ps delay with 3ps resolution. The delay cell occupies an active area of 0.0378mm^2, and dissipates 80mW of power at its maximum delay setting. The delay/size of our implementation is 13 ns/mm^2, is at least 2x more than other delay circuits reported in literature which makes it quite suitable for ultra wideband operations that needs large amounts of delay.
Implemented 9th order Gm-C All pass Filter
Implemented delay element including calibration circuitry
Layout of the delay element, occupying area of 0.0378 mm2
Group Delay and Time Domain Plots with Monte Carlo Runs
A 2mm, 16 channel, 6.5GHz BW, Beamforming receiver in 65nm CMOS process
Duration: July 2016 - Sep 2016
Guide: Prof. Nagendra Krishnapura, Electrical Engineering, IIT Madras
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Abstract:
Wideband beamforming receivers necessary for directional signal reception and rejecting spatial interferers require sharp spatial selectivity which needs large number of antennas. This requires each delay element to have large, wideband, delays with fine resolution. Tapped delay line or LC filter based elements occupy a large area making large on-chip arrays infeasible. Compact active true-time-delay lines can be realized using a high order Gm-C all-pass filter(APF) based on a singly-terminated ladder filter. Increased mismatch at small area is combated by calibrating all gms at startup. Proposed calibration enables 5x area reduction for the same mismatch. We demonstrate the first silicon implementation of 16 antenna element beamforming array using the 50-500 ps compact delay element and 16dB gain LNAs. The architecture occupies 2mm2, provides 54o scanning angle with 2.5o resolution, and has a minimum mainlobe beam width of 12.6o. The narrow beam pattern generated has a very good spatial sensitivity and is used in high resolution RADAR and wireless imaging. The delay element can also be used in the design of a UWB RF Camera for high resolution imaging with 41x41 active pixels.
Design of 16 element beamforming receiver array
Comparison Table of the Beamformer with other architectures
Design of 4x4 array UWB RF Detector
Analog to Information - Ultra Low Power Voice Command Detection and System Wake up Device
Duration: Oct 2016 - Present (Ongoing Project)
Guide: Dr. Mahesh Mehendale, Kilby Research Labs, Texas Instruments India
Abstract:
The primary function of this device is to provide ultra-low power “always on” voice command detection and system wake-up. It is intended to work for distance applications (1-5m) as well as mobile applications. It can process up to 14 voice-band features and can hold up to one user-independent and four user-dependent command enrollments in the memory, which can reloaded or exchanged on the fly. I have designed and tapped-out of state of the art low power -38dBV/Pa sensitivity low power microphone amplifier with zero input common mode which feeds the analog front end of the voice wake up system. Specifications achieved from layout extracted netlist: Gain of 6dB, THD of 0.5% in audio bandwidth of 20Hz to 20KHz, SNR of 62dB, PSRR of -50dB and current consumption of 20µA. I am currently working on processing 14 voice band features and designing analog neural network implementation of filter banks used in analog front end of voice command detection system to reduce power.
Layout and top level diagram of tapped-out Microphone
IIT Madras Student Satellite Project
Duration: Aug 2012 - Feb 2014
Mentor: Dr. Harishankar Ramachandran, Electrical Engineering, IIT Madras
What is IITMSAT?
IITMSAT is a student satellite initiative to design and build a Nano satellite which will study the features of plasma in the upper ionosphere to characterize its relation with earth-based phenomena like seismic activity. This unique study is made through a Space Based Proton- Electron Energy Detector (SPEED) payload on-board the satellite capable of measuring the energy spectrum of plasma. The satellite is currently in its engineering phase and is expected to launch in 2015.
I have been involved in the development of SPEED for more than 18 months. A summary of the areas I have worked on are:
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Design of Analog Front End Electronics of SPEED
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Board Design of 3 parallel FEE Chains
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Testing of designs and integrating different blocks of SPEED
As part of this project, I have participated / presented in many reviews consisting of faculty and ISRO committees. I was also involved in several group visits, including the Indian Space Reseach Organization (Bangalore) and Indian Institute of Space Science and Technology (Trivandrum).
My work has culminated in many technical documents on a variety of aspects detailed above. A presentation on few of the above topics can be viewed here.
Development of SPEED Prototype:
In June 2013, I along with five other students interned at the Scientific Satellite Instrumentation Facility at ISITE, Bangalore - a division of the Indian Space Research Organization for 2 months during our Summer break. We worked under the guidance of Dr. Manju Sudhakar (Scientist, Space Astronomy Division) and the other scientists at ISITE, to develop a prototype of SPEED that would demonstrate the end-to-end functionality of the detector system. We developed a prototype that consisted of a Photo-multiplier tube (to detect scintillations), a Charge-sensitive pre-amplifier and associated analog electronics (to convert the current generated by the Photo-multiplier tubes to sensible voltage signals that can be processed further), and a digital electronics system (to extract the intensity of the scintillations). The prototype faithfully demonstrated its function as a photon counter.
3-D rendered view of IITMSAT, with the SPEED payload instrument on top and the inverted F- antenna surrounding it
A 3-D view of the SPEED payload housed in a specially designed aluminium casing, with routing assemblies for wavelength -shifting (WLS) fibers, Photomultiplier tubes and the electronics PCB's.
Charge-sensitive preamplifier circuit with a gaussian shaper. The input to the circuit is a Photo-multiplier tube current output.
A block-diagram describing the prototype developed at ISITE which demonstrated the end-to-end functionality of the detector. CSPA - Charge Sensitive Pre-amplifier | AD829 - An IC functioning as a buffer | LM319 - An Op-Amp functioning as a comparator | PH300 - (Peak Hold Detector) A hybrid circuit to hold the amplitude of a voltage pulse
Board Layout of CSPA circuit with a gaussian shaper.
Thick Oxide MOS Capacitors as Wireless Radiation Dose Sensors
Duration: May 2014 - July 2014
Mentor: Dr. Dimitrios Peroulis, Electrical Engineering, Purdue University, Indiana, United States
Abstract:
The threat of an attack with radiological or nuclear materials has significantly increased over the past decade. It is essential for continuously monitoring the movement of radioactive materials using wireless dose sensors. In particular for medical applications, wireless sensors are used for measuring radiation dose during cancer radiotherapy. This wireless dose sensor can be realized with a solid state RADiation sensitive CAPacitor (RADCAP) mounted on a resonant patch antenna. These sensors are calibrated such that the change in capacitance, due to a build-up of oxide trapped charges can be used to estimate radiation dose. From the resonant frequency, the capacitance can be extracted which can be mapped back to estimate the radiation dose level. The capacitor acts as both radiation dose sensor and resonator element in the passive antenna loop. Since the MOS capacitor is used in passive state, characterizing various parameters that affect the radiation sensitivity is essential. Oxide processing technique, choice of insulator material, and thickness of the insulator, critically affect the dose response of the sensor. For high radiation sensitivity, I have simulated thicker oxide new geometry MOS capacitors which could accommodate more amount of charge. I have used TAURUS MEDICI Synopsys tool for the simulations of MOSCAP with various oxide charges. A capacitor with a 2mm x 2mm Aluminum metal over a 400nm SiO2 film and on a 20ohm-cm Si wafer with a thickness of 0.5 mm has been fabricated, verified with simulations and tested for radiation doses.
Device Tracker
Duration: May 2012 - July 2012
Mentor: Dr. Harishankar Ramachandran, Electrical Engineering, IIT Madras
Abstract:
The devices like Cars, Laptops and Mobiles could be integrated with Transmitters which transmit a RF signal. The Device Tracker which we designed is a Hand held unit that receives the RF signal. At a fixed distance when the user sweeps the device in an arc there should be a notification of the direction of the RF source via a light up LED. The Device also has a 10 LED Display signal strength indicator which gives the distance between the transmitter and receiver. The device built can be used for tracking lost devices and also for Hunting and Games.
Hand Held Device to track the Car.
Design of Direction Finding Device
Text Extraction from Documents
Duration: Dec 2013 - Jan 2014
Cognizant Technology Solutions
Abstract:
Many a times, we need to extract text from documents for future use. I worked on Image Processing; main goal was to extract text from a scanned form or document. Developed the text detection algorithm and implemented it in C++ using Visual Studio and
OpenCV. The algorithm has been verified on various test documents containing text.
Course Projects
I've done several other course projects in the 5 years at IIT-Madras.
1. Fully differential two stage opamp and Constant Voltage Generator using Band Gap Reference in 180nm CMOS process
Course Guide: Prof. Nagendra Krishnapura, Electrical Engineering, IIT Madras
Designed amplifier using two stage miller compensated opamp with gain of 2, 3dB bandwidth of 5.96MHz, phase margin of 60 degrees. Noise analysis and slew rate analysis were performed for the amplifier. Implemented band gap reference circuit with minimum voltage variation from 0 to 100 C.
2. Standard cell design and Characterization in 180nm technology
Course Guide: Prof. Vinita Vasudevan, Electrical Engineering, IIT Madras
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Designed 4 input NAND Gate, NOR2x1 and CMOS inverter and used MAGIC to layout the standard cells.
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Characterized standard cell delay for all possible input combinations and different load capacitances.
3. Design of Spectrum Analyzer
Course Guide: Prof. Shanthi Pavan, Electrical Engineering, IIT Madras
Designed and tested a Spectrum Analyzer from transistor level which is capable of displaying the spectrum of input signal from 0.5 to 5 KHz when connected to an oscilloscope in time mode.
4. Hardware modeling and FPGA implementation
Course Guide: Prof. Nitin Chandrachoodan, Electrical Engineering, IIT Madras
Designed 8 bit processor with basic integer arithmetic operations (add/sub & mul/div) and Boolean operations. Implemented
Control Unit & ALU using HDL, RAM & ROM using on chip memory elements.
5. Implementation of different multiplication techniques on Spartan 3E FPGA Board
Course Guide: Prof. Nitin Chandrachoodan, Electrical Engineering, IIT Madras
Simple signed multiplier, Pipelined multiplier using the IP core generator and the sequential multiplier are implemented and
tested using automated test benches to verify correct operation. Analyzed the synthesis reports to differentiate the number of
LUTs, registers, hardware resources used in implementing different multiplier techniques.
6. Implementation of shifted DQPSK using GNURadio
Course Guide: Prof. Andrew Thangaraj, Electrical Engineering, IIT Madras
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Implemented the model of communication of a (Pi/4)DQPSK and (Pi/8) Differential 8 PSK in GRC
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The model consisted of modulation of data, implementation of root-raised cosine filters, up-conversion to pass-band, transmission, down-conversion to baseband and slicing.
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Also implemented sub-carriers in the given bandwidth with different channels carrying different modulation schemes such as DQPSK, 16-QAM, 64-QAM etc.
7. Leaf Press Machine Design
Course Guide: Prof. Sujatha Srinivasan, Mechanical Engineering, IIT Madras
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Automated the existing manually operated Leaf press machine in a company (Twin Twigs), operated by physically handicapped using At mega Microcontrollers and High Power DC Motors.
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Wrote the assembly language code on Arduino IDE to suit the requirement
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Proposed a design to replace the existing mould by four small moulds and thereby increasing the productivity.
8. Simulator for Eye Condition – Retinopathy of Prematurity
Course Guide: Dr. Namita Jacob, Perkins International
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Designed a hand held portable Eye-frame to test visual acuity, visual field loss and Night blindness.
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Designed electronics to blind the eye with light to simulate peripheral field loss and Night blindness.
9. Simulation of MOSFET B-SIM Model
Course Guide: Dr. Karmalkar, Electrical Engineering, IIT Madras
Programmed the current vs voltage characteristics of MOSFET based on the Surface Potential Based model in python. These characteristics are used to extract the parameters for the B-SIM model and obtain the simulation results for this model.
10. Rectilinear Polygon Processing
Course Guide: Dr. G Venkatesh, Electrical Engineering, IIT Madras
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Given a set of rectilinear polygons, developed an algorithm to find out the all the equipotential regions (collection of all polygons which are connected) and implemented the algorithm in C++.
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Passed all the test cases given by three other teams by running their test inputs on our code.
11. Fabrication and characterization of a solar cell
Course Guide: Dr. Soumya Dutta, Electrical Engineering, IIT Madras
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Fabricated Organic and Silicon solar cells using fabrication facility available at Microelectronics Lab in IIT Madras.
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Characterized the solar cell to find the efficiency, fill factor and other important parameters.
12. Implementation of SPICE circuit simulator using C program
Course Guide: Dr. Harishankar Ramachandran, Electrical Engineering, IIT Madras
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Developed a program that accepts a standard SPICE net list with resistors, capacitors and inductors
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Results of the program include DC voltages, current and transfer functions.
13. Water Level Indicator for house hold purpose
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Designed and built a water level indicator using sensors and microcontroller which displays the percentage of water in the tank.